Multichip semiconductor package

ABSTRACT

A multichip semiconductor package and method of making is provided that has a plurality of semiconductor chips fabricated in electrical isolation one from another integrally on a singular coextensive substrate useful for numerous and varied semiconductor chip applications. The semiconductor chips, instead of being singulated into a plurality of single-chip packages, are kept as integrally formed together and are thereafter electrically connected together so as to form a larger circuit. Encapsulation follows so as to form a single, multichip package. Common signals of the plurality of semiconductor chips are bussed together in electrical common across the substrate to a common electrode suitable for electrically providing the signal to another, external circuit, such as a PWB. The common bussing is achieved by conductive leads disposed across the substrate in pair sets having an extended portion that accommodates the common electrode in contact therewith. The common electrode contacts the conductive lead through an opening formed in the encapsulant that surrounds the substrate. The extended portions of each conductive lead are staggered with respect to the extended portion of the conductive lead in the same, or juxtaposed, pair set. In this manner, multiple electrodes are available for close proximity positioning while, simultaneously, avoiding electrical shorts amongst the pair sets.

BACKGROUND OF THE INVENTION

This is a continuation of U.S. patent application Ser. No. 09/032,191,filed on Feb. 27, 1998, which is incorporated herein by reference.

1. The Field of the Invention

The present invention relates generally to multichip semiconductorpackages and particularly relates to an improved semiconductor packagehaving a plurality of semiconductor chips fabricated as a singularcoextensive substrate and to its method of making.

2. The Relevant Technology

Multichip packaging is one of the fastest growing disciplines in thechip packaging industry. Initially, the multichip package came intoexistence for applications requiring numerous and varied circuitsconfigured into a least amount of space, such as with mainframes andsupercomputers. Since then, multichip packages have transcendedtraditional boundaries and moved into conventional single-chipapplications because they characteristically possess reduced weight andsize per each circuit, increased reliability and increased electricalperformance. As such, multichip packages are now regularly employed inconsumer electronics, medical and avionic devices, and in the automotiveand aerospace industries. Multichip packages also find particularusefulness in telecommunication applications because of their highbandwidth performance.

In general, conventional multichip packages are available in one of twovarieties. One has two or more bare chips bonded directly to a multichipsubstrate and the other, the most commercially predominant package, hastwo or more pre-packaged single-chips in their respective single-chipcarriers and bonded to a multichip substrate. Although the formervariety enjoys advantages over the latter, both varieties remain boundby single-chip constraints because of their dependence upon either abare, or packaged, single-chip. As such, both varieties frequently sharecommon problems with their single-chip counterparts.

For example, in response to an industry-wide demand for high lead countsand small “footprints,” i.e., the arrangement of electrical contacts onthe printed circuit board to which the chip package is ultimatelyconnected, single-chip packages became available in Ball Grid Array(BGA), “flip-chip” and “chip-scale” packages. The problem, however, isthat these singular-chip packages have external electrodes, which can besolder balls, that are directly attached to contacts on the surface ofthe semiconductor chip. As semiconductor chips are continually reducedin size, the arrangement of the external electrodes must also becontinually reconfigured into a correspondingly smaller size. In turn,the footprint on the printed circuit board must also be continuallyreconfigured. This problem is even further amplified with multichippackages because footprint reconfiguration also needs to occur on themultichip substrate itself to which the single-chip packages areattached. It is, therefore, desirous to eliminate the continualreconfiguring of the footprint of the multichip package and therearrangement of the multichip substrate.

In a separate and distinct discipline, Wafer Scale Integration (WSI)techniques have been used to fabricate various other multichiparrangements. Yet WSI often utilizes 800, or more, semiconductor chipsas a single multichip which, in effect, is too cumbersome, if notprohibitive, to encapsulate into a package format. The large size isalso inefficient for applications requiring relatively few semiconductorchips, around 64 or less, because of the high wiring density used in WSIwirebonding operations and the surplus unneeded chips. Effective testingof each individual chip with WSI is also problematic because of thelarge number of chips. Additionally, WSI techniques frequently requireexpensive photolithography equipment, not typically utilized withsingle-chip packages, to transfer a circuit image onto a multichipsubstrate.

A need exists for a multichip package that overcomes the foregoingproblems.

SUMMARY OF THE INVENTION

In accordance with the invention as embodied and broadly describedherein, a novel multichip semiconductor package, and method of making,is provided that has a plurality of semiconductor chips fabricated inelectrical isolation, one from another, as a singular coextensivesemiconductor substrate useful for numerous and varied semiconductorchip applications. In the context of this document, the term“semiconductor substrate” is defined to mean any construction comprisingsemiconductive material, including but not limited to bulksemiconductive material such as a semiconductive wafer, either alone orin assemblies comprising other materials thereon, and semiconductivematerial layers, either alone or in assemblies comprising othermaterials. The term “substrate” refers to any supporting structureincluding but not limited to the semiconductor substrates describedabove. As such, silicon on insulator and silicon on sapphire are withinthe definition of substrate.

Once fabricated, instead of being singulated into a plurality ofsingle-chip packages, the semiconductor chips are kept integrally on thesubstrate. The semiconductor chips, which are electrically isolated onefrom another, are then wired so as to be electrically connected togetherto form a larger circuit, such as to expand a memory circuit, and thenencapsulated and processed into a single, multichip package.

In a preferred embodiment, a multichip package has a plurality ofelectrically isolated semiconductor chips integrally formed on a unitarysemiconductor substrate. A plurality of conductive leads electricallyconnect the electrically isolated semiconductor chips. A compoundsubstantially encapsulates at least a portion of the semiconductorsubstrate, and a plurality of electrodes extend through the compound tomake contact with the conductive leads.

In another preferred embodiment, a multichip semiconductor packageincludes a plurality of electrically isolated semiconductor chips thatare integrally formed on a unitary semiconductor substrate, eachsemiconductor chip having an active device formed thereon. The multichipsemiconductor package also includes a plurality of bond pads, each bondpad being electrically connected one per each active device. A pluralityof conductive leads electrically connect the electrically isolatedsemiconductor chips, where each conductive lead is electricallyconnected one per each bond pad. A compound substantially encapsulatesat least a portion of the semiconductor substrate, the bond pads, andthe conductive leads. There are also a plurality of solder balls, whereeach solder ball extends through the compound to make contact with arespective one of the conductive leads.

In yet another preferred embodiment, the common signals of the pluralityof semiconductor chips are bussed in electrical common across thesubstrate to a common electrode suitable for electrically providing thesignal to another, external circuit, such as a Printed Wiring Board(PWB). The common bussing is achieved by conductive leads disposedacross the substrate in pair sets having an extended portion thataccommodates the electrode in contact therewith. The electrode contactsthe conductive lead through an opening formed in the encapsulant thatsurrounds the substrate. The extended portions of each conductive leadare staggered with respect to the extended portion of the conductivelead in the same, or juxtaposed, pair set. In this manner, multipleelectrodes are available for close proximity positioning while,simultaneously, avoiding electrical shorts amongst the pair sets.

In an alternate embodiment, the conductive leads extend beyond theencapsulant to facilitate testing or improve manageability of thepackage during the manufacturing process. The conductive leads, afterthe testing or manufacturing, may then be sheared flush to avoidmechanical interferences between the external circuit, i.e., the PWB, orto create a stronger and thicker multichip package.

A method of making the inventive multichip package includes providing aunitary semiconductor substrate and integrally forming a plurality ofelectrically isolated semiconductor chips on the unitary semiconductorsubstrate. There is then formed a plurality of conductive leads thatelectrically connect the electrically isolated semiconductor chips. Acompound then substantially encapsulates at least a portion of thesemiconductor substrate, and a plurality of electrodes are formed so asto extend through the compound to make contact with the conductiveleads.

Another method of making the inventive multichip package includesproviding a unitary semiconductor substrate. A plurality of electricallyisolated semiconductor chips are integrally formed on the unitarysemiconductor substrate each having an active device formed thereon. Aplurality of bond pads are formed so as to make electrical connectionsfrom each bond pad to one of the active devices. Electrical connectionsare also formed to electrically connect the electrically isolatedsemiconductor chips with a plurality of conductive leads. Eachconductive lead is electrically connected one per each bond pad. Acompound is formed so as to substantially encapsulate at least a portionof the semiconductor substrate, the bond pads, and the conductive leads.A plurality of solder balls are formed so as to extend through thecompound to make contact with a respective one of the conductive leads.

A still further method of making the inventive multichip packageincludes a singular substrate being fabricated with a plurality ofelectrically isolated semiconductor chips integrally formed thereon.Centrally located bond pads are provided for connection with the activedevices of the chips by exposing the bond pads through apertures in aninsulating or passivation layer which forms the upper surface of eachchip. Conductive leads are positioned over the chips and are extended inlength to an area near the bond pads for wire bonding connectionsthereto. The conductive leads are attached to an upper surface of thechips with Lead-Over-Chip (LOC) tape. The multichip package is at leastpartially encapsulated with a compound, and openings are formed in thecompound to at least partially expose the conductive leads. Electrodesare made to contact the conductive leads that are exposed through theopenings in the compound.

These and other features of the present invention will become more fullyapparent from the following description and appended claims, or may belearned by the practice of the invention as set forth hereinafter.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more fully understand the manner in which the above-recitedand other advantages of the invention are obtained, a more particulardescription of the invention will be rendered by reference to thespecific embodiments thereof which are illustrated in the appendeddrawings. Understanding that these drawings depict only typicalembodiments of the invention and are not therefore to be considered tobe limiting of its scope, the invention in its presently understood bestmode for making and using the same will be described and explained withadditional specificity and detail through the use of the accompanyingdrawings in which:

FIG. 1 is a top view of a multichip package as taken from beneath a toplayer of encapsulating material according to one embodiment of thepresent invention;

FIG. 2 is a cross section view of the multichip package of FIG. 1 takenalong line 2-2;

FIG. 3 is a cross section view of a multichip package having conductiveleads extending beyond the encapsulating compound according to anotherembodiment of the present invention;

FIG. 4 is a cross section view of a multichip package having conductiveleads sheared flush with the encapsulating compound according to afurther embodiment of the present invention; and

FIG. 5 is a top perspective view of a multichip package with a cut-awayview through the encapsulating material to reveal eight semiconductorchips and a plurality of common busses across the semiconductor chipsaccording to a still further embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates to a novel multichip semiconductor packagehaving a plurality of semiconductor chips fabricated as a singularcoextensive substrate and to its method of making.

With reference to FIGS. 1 and 2, a multichip semiconductor package,depicted generally as package 20, has a plurality of semiconductor chips22 each arranged in electrical isolation, one from another, adjacentlyalong a terminal boundary 24 thereof as a singular coextensive substrate26. Chips 22 are integrally formed on substrate 26 which may be asemiconductor material such as gallium arsenide, silicon, or can besilicon on sapphire, silicon on insulator. Substrate 26, preferably amonocrystalline silicon wafer, has the individual semiconductor chips 22fabricated thereon by conventional techniques currently employed in themanufacture of single-chip packages. The difference, however, is thatinstead of dividing individual chips 22 into discrete single-chippackages by a singulation process performed upon the wafer, theindividual chips, though electrically isolated one from another, arethen electrically connected and then encapsulated into a singularmultichip package 20 as described hereinafter.

In particular, attached to semiconductor chip 22, preferably bylamination techniques using a lead-over-chip (LOC) adhesive 27, a leadlocking tape 29, and a wire bonding segment 31, is a lead frame 28 towhich electrodes 30 are electrically contacted. Lead frame 28 isprovided, one per package 20, to yield electrical continuity betweenelectrodes 30 and the internal devices of semiconductor chip 22 by wayof a singular conductive lead 32, one per each electrode 30. Electrode30 is connected to conductive lead 32 at a selected position along alength thereof. It should be appreciated that each selected position ofconnection between each electrode 30 and each respective conductive lead32 yields an arrangement of electrodes 30 about package 20, knowncommonly as a package footprint. The package footprint has acorresponding footprint on a PWB (not shown), for example, that allowsfor completion of an electrical circuit between the internal devices ofpackage 20 and the circuit fabricated on the PWB when the two footprintsare electrically connected. Advantageously, since each electrode 30 isnot directly connected to semiconductor chip 22 by way of bond pads orwiring traces, as are conventional BGA's, flip-chips, and chip-scalepackages, the package footprint can remain consistent in size and shapedespite continual size reductions in individual semiconductor chips.This is possible because the length of conductive lead 32 acts as anelectrical bus from the internal devices in semiconductor chips 22 tothe position of electrode 30. As semiconductor chip 22 is reduced insize, the dimensions of conductive lead 32 are adjusted and electricalcontinuity remains bussed out to electrode 30. Typically, as in FIGS. 3and 4, conductive leads 32 are plated at an electrode bond area 58 witha thin layer of metal to improve the strength and conductivity betweenelectrode 30 and conductive lead 32. Since electrodes 30 can be solderballs, the metal composition thereof is preferably gold,palladium/nickel, or tin.

In the preferred embodiment of FIG. 1, the package footprint has rows 35of electrodes 30 disposed across semiconductor chips 22 in twosubstantially parallel lines 34, 36 with each individual electrode 30being contacted, one per each conductive lead 32, along an extendedportion 38 of the substantially rectangular conductive lead. Theextended portion is present on conductive lead 32 because the width ofthe remainder of conductive lead 32, while a cost effective use ofmaterials, is too thin to fully accommodate electrode 30. It should beappreciated that electrode 30 only exceeds the width of conductive leads32 to the extent necessary to prevent mechanical bonding failures, suchas solder joint failures.

Conductive leads 32 are preferably arranged in sets of pairs 40, 42across semiconductor chips 22. Each pair set 40, 42 is arranged inrelatively close proximity. Each extended portion 38 of each conductivelead 32 is staggered with respect to another extended portion 38 ofconductive lead 32 in the same or juxtaposed to pair set 40, 42. In thismanner, multiple electrodes 30 are available for close proximitypositioning while, simultaneously, avoiding electrical shorts in andamongst pair sets 40, 42 which would otherwise occur with electrodes ofthe size and shape depicted if electrodes 30 were all placedside-by-side in a linear fashion. Yet, it should be appreciated thatchanges in the size and shape of electrode 30 are contemplated thatwould yield other distinct package footprints without altering thefabrication or effectiveness of singular coextensive substrate 26 havinga plurality of semiconductor chips 22 integrally formed thereon. Forexample, it is contemplated that the portion of electrode 30 contactingconductive lead 32 can be reduced in area to a size that does not exceedthe pitch of conductive leads 32, thereby making extended portions 38superfluous. It is also contemplated that extended portions 38 could bealternated at opposite ends of their respective pair sets 40, 42 orarranged in other ways that maintain a cost effective conductive lead 32while preventing electrical shorts.

The plurality of semiconductor chips 22 are electrically bondedtogether, along a periphery 43 and a central portion 44 of package 20,by way of bond pads 45 and bond wires 46 to form, for example, a largerpackage circuit, or as in a preferred embodiment, to expand the overallmemory of semiconductor chips, such as DRAM semiconductor chips. It isto be appreciated that the bond pads can be any of the various terminalsformed near the surface of semiconductor chip 22 through whichelectrical connections can be made between the active devices in chip 22and external circuits. Bond wires 46 are preferably connected along aterminal end 48 of conductive leads 32 at a respective terminal end 48,as depicted in FIGS. 3 and 4. Typically, conductive leads 32 are platedat a wire bond area with a thin layer of metal suitable for wirebonding, such as gold, silver or palladium/nickel to improve thestrength and conductivity of the bond between conductive leads 32 andbond wires 46.

Package 20 is encapsulated in a compound 50 which has openings formedtherein that partially expose conductive leads 32 at the selectedconnection positions, which is preferably electrode bond area 58. Theopenings are sized and shaped according to the selected size and shapeof electrodes 30 and are adjustable to correspond with changes in theselected size and shape. Compound 50, often a molding compound, isgenerally an electrically insulating formulation used to distributepower, dissipate heat and protect the active devices therein fromthermomechanical stresses and pollutants found in the operatingenvironment. Preferably, compound 50 is a thermosetting epoxy resin, butmay also be silicon, phenolic, or polyeurethane. The composition ofcompound 50 is generally derived from a balance of numerous engineeringfactors including the cost of manufacturing, production volume, expecteduse environment, expected use market and other related considerations.It is also contemplated that compound 50 may be a polyimide compounduseful as an alpha barrier.

In the preferred embodiment depicted in FIG. 2, conductive leads 32 havebeen fully encapsulated within compound 50. There are other usefulembodiments for conductive leads 32. For example, in FIG. 3, conductiveleads 32 are extended out from compound 50 to facilitate chip testingand also to enable package 20 to be easily maneuvered during themanufacturing process. It is also contemplated that conductive leads 32could remain attached to semiconductor chips 22 without any of, or as acompliment to, electrodes 30 so that a signal could be taken directlytherefrom as package 20 is used in either a surface mount, orthrough-hole capacity. In FIG. 4, conductive leads 32 have been shearedflush with compound 50 after either testing or manufacturing in order tocreate a thicker and stronger terminal portion of package 20, or toremove any potential mechanical interferences from conductive leads 32.

With reference to FIG. 5, package 20 has eight semiconductor chips 22adjacently arranged in electrical isolation, in the manner previouslydescribed, with conductive leads 32 again disposed in pairs 40, 42across substrate 26. Instead of the semiconductor chips 22 beinginterconnected by discretely wiring conductive leads 32 thereof,conductive leads 32 in this embodiment are bussed common to eliminatehigh wiring density within package 20 and to provide for redundantback-up in the event a semiconductor chip 22 has a bad, or deteriorated,signal line. The common bussing also allows for common addresses (A0, A1. . . An), common data out (DO), common data queries (DQ) or voltagesteady state (Vss) electrodes, for example, to be fabricated togetherelectrically, thereby eliminating electrode repetition and reducingmaterial costs. Although some signal lines are independent and cannot,for various reasons, be bussed common, such as individual chip enables(CE) and row address strobes (RAS), those signal lines can be groupedtogether into common areas for efficaciously facilitatinginterconnection with an external circuit, such as a PWB. For example, aplurality of wiring banks 54 are configured about the periphery ofpackage 20 along three sides and about the interior of package 20 inrows 35 having two substantially parallel lines 34, 36 of electrodes 30.It should be understood that wiring banks 54 could all be groupedtogether, but to do so would be at the expense of increasing wiringdensities and creating manufacturing difficulties such as havinginadequate wiring angles for attaching bond pads 45 to conductive leads32. Yet, alternatives exist that will effectively accommodate thegrouping of wiring banks 54 about package 20 that provide ease ofelectrical connection with other external circuits and are within thespirit of the present invention.

In response to industry demands for thin packages, this embodimentdepicts compound 50 as being disposed upon top side 60 of substrate 26while bottom side 62 remains uncovered. It is possible, however, toforego disposing any of compound 50 on substrate 26. It is preferred,however, that at least a partial encapsulation of compound 50 is appliedabout substrate 26 to prevent undesirable conditions, such as electricalshorting.

Although the arrangement of the discrete electrically isolatedsemiconductor chips 22 has heretofore been described as either being twoor eight in number and fabricated in adjacent arrangement with oneanother within substantially rectangular packages, one skilled in theart should appreciate that still other embodiments exist that are withinthe express teachings of the present invention. For example, it iscontemplated that semiconductor chips 22 range in preferred quantitiesfrom 2 to 8 but may also be as large as 64 or more. The arrangement ofsemiconductor chips 22 may also be fabricated into various otherpatterns so long as chips 22 remain as discrete, electrically isolatedunits integrally formed on singular coextensive substrate 26.

The steps of fabrication of multichip package 20 include a singularsubstrate 26 being fabricated with a plurality of electrically isolatedsemiconductor chips 22 thereon. Instead of a singulation process ofsawing the individual chips into discrete single-chips for packaging,chips 22 are kept as integrally formed electrically isolated elementsthat are thereafter electrically connected together. Next, bond pads 45are provided to connect to the active devices (not shown) by exposingbond pads 45 through apertures in an insulating or passivation layerwhich forms the upper surface of chip 22.

Conductive leads 32, which form the inner portion of the singular leadframe 28, are then positioned over chips 22 and extended in length to anarea near bond pads 45 for wire bonding connections thereto. Conductiveleads 32 are usually prefabricated with a plating of a thin layer ofsuitable metal at terminal end 48 but can also be plated afterencapsulation. In sequence, conductive leads 32 are connected to anupper surface of chips 22 with LOC adhesive 27. For a detaileddescription thereof, refer to U.S. Pat. No. 5,286,679, issued toFarnworth et al., which is incorporated herein by reference.

Once connected, package 20 is at least partially encapsulated withcompound 50 and openings are formed therein to at least partially exposeconductive leads 32, where exposure preferably is at electrode bond area58. Also, conductive leads 32 are usually prefabricated with a platingof a thin layer of suitable metal at electrode bond area 58. Afterencapsulation, any remaining resin residue that is present on the wire46 or electrode bond area 58 is removed by electrolytic or mechanicaldeflash processes known in the art.

Lastly, electrodes 30, preferably solder balls, are bonded to electrodebond areas 58 through openings in compound 50. The solder balls may beattached, as is known in the art, by coating the solder balls or bondareas 58 with flux, placing the solder balls on electrode bond area 58through the openings with conventional pick and place or shaker/hopperequipment, and reflowing the balls in place using an infrared or hot airreflow process. The excess flux is then removed with an appropriatecleaning agent. In this manner, the solder balls are electrically andmechanically connected to conductive leads 32 to form electrodes 30external to compound 50. Other processes may also be used to formelectrodes 30. For example, electrodes 30 may be “plated up” usingconventional plating techniques rather than using the solder balltechniques as described above. The completed multichip semiconductorpackage 20 can then be assembled to a printed circuit board or the likeusing conventional surface mount or through hole processes andequipment.

While there has been shown and described a novel multichip packagehaving a package footprint configured independently of the size of theindividual semiconductor chips therein that is made with conventionalleaded chip packaging processes and equipment, it is to be appreciatedthat the present invention may be embodied in other specific formswithout departing from its spirit or essential characteristics. Thedescribed embodiments are to be considered, in all respects, only asillustrative and not restrictive. The scope of the invention is,therefore, indicated by the appended claims rather than by the foregoingdescription. All changes which come within the meaning and range ofequivalency of the claims are to be embraced within their scope.

1-20. (canceled)
 21. An apparatus for supporting a microelectronicsubstrate, comprising: a support member having a support surfaceconfigured to carry a microelectronic substrate; a first connectionstructure carried by the support member and configured to remaindecoupled from the microelectronic substrate when the support membercarries the microelectronic substrate, the first connection structurehaving a first bond site configured to receive a flowable conductivematerial, the first connection structure further having a first numberof first elongated members connected to and extending outwardly from thefirst bond site, wherein none of the first elongated members isconfigured to be electrically connected to the microelectronicsubstrate; and a second connection structure carried by the supportmember, the second connection structure having a second bond siteconfigured to receive a flowable conductive material, the secondconnection structure being configured to be coupled to themicroelectronic substrate when the support member carries themicroelectronic substrate, the second connection structure furtherhaving a second number of second elongated members extending outwardlyfrom the second bond site, the second number being the same as the firstnumber.
 22. The apparatus of claim 21 wherein each of the firstelongated members is configured to receive at least a portion of theflowable conductive material and wherein each of the second elongatedmembers is configured to receive at least a portion of the flowableconductive material.
 23. The apparatus of claim 21 wherein the secondconnection structure has a third bond site configured to be wire bondedto the microelectronic substrate when the microelectronic substrate iscarried by the support member, and wherein at least one of the secondelongated members extends between the second and third bond sites. 24.The apparatus of claim 21 wherein the first conductive structureincludes two first elongated members extending away from opposite sidesof the first bond site.
 25. The apparatus of claim 21 wherein the firstconnection structure includes at least one electrically conductivemetallic material.
 26. The apparatus of claim 21 wherein one of thefirst elongated members is shorter than another of the first elongatedmembers.
 27. The apparatus of claim 21 wherein the first bond siteincludes a solder ball pad, and wherein the apparatus further comprisesa solder ball disposed on the solder ball pad.
 28. The apparatus ofclaim 21, further comprising: a first solder ball disposed on the firstbond site and having a first size and shape; a second solder balldisposed on the second bond site and having a second size at leastapproximately the same as the first size, and a second shape at leastapproximately the same as the first shape; and a microelectronicsubstrate carried by the support member, the microelectronic substratebeing electrically coupled to the second connection structure and beingelectrically isolated from the first connection structure.
 29. Theapparatus of claim 21 wherein the first connection structure and thesecond connection structure each have two elongated members.
 30. Theapparatus of claim 21 wherein each of the first and second elongatedmembers has an axis along which the member is elongated and wherein eachmember has a width transverse to the axis, further wherein the widths ofall the elongated members on the support member are approximately equal.31. The apparatus of claim 21, further comprising: a first solder balldisposed on the first bond site and projecting away from the first bondsite by a first distance; and a second solder ball disposed on thesecond bond site and projecting away from the second bond site by asecond distance at least approximately the same as the first distance.32. An apparatus for supporting a microelectronic substrate, comprising:a support member having a support surface configured to carry amicroelectronic substrate; a first bond site carried by the supportmember and configured to remain decoupled from the microelectronicsubstrate when the support member carries the microelectronic substrate;first elongated members connected to and extending outwardly from thefirst bond site; a first portion of a flowable conductive materialdisposed on the first bond site, the first portion of the flowableconductive material projecting from the first bond site in a directiongenerally normal to the first bond site by a first distance; a secondbond site carried by the support member and configured to beelectrically coupled to the microelectronic substrate when the supportmember carries the microelectronic substrate; second elongated membersextending outwardly from the second bond site; and a second portion of aflowable conductive material disposed on the second bond site, thesecond portion of the flowable conductive material projecting from thesecond bond site in a direction generally normal to the second bond siteby a second distance at least approximately equal to the first distance.33. The apparatus of claim 32 wherein the first bond site has a total ofa first number of first elongated members and the second bond site has atotal of a second number of second elongated members, and wherein thefirst number is the same as the second number.
 34. The apparatus ofclaim 32, further comprising a third bond site configured to be wirebonded to the microelectronic substrate when the microelectronicsubstrate is carried by the support member, and wherein at least one ofthe second elongated members extends between the second and third bondsites.
 35. The apparatus of claim 32 wherein at least part of the firstportion of the flowable conductive material extends along the firstelongated members, and wherein at least part of the second portion ofthe flowable conductive material extends along the second elongatedmembers.
 36. The apparatus of claim 32 wherein the first elongatedmembers include two first elongated members extending away from oppositesides of the first bond site.
 37. The apparatus of claim 32 wherein thefirst elongated members include at least one electrically conductivemetallic material.
 38. The apparatus of claim 32 wherein the first bondsite includes a solder ball pad, and wherein the flowable conductivematerial includes a solder ball disposed on the solder ball pad.
 39. Theapparatus of claim 32, further comprising: a first solder ball disposedon the first bond site; a second solder ball disposed on the second bondsite; and a microelectronic substrate carried by the support member, themicroelectronic substrate being electrically coupled to the second bondsite and being electrically isolated from the first bond site.
 40. Amicroelectronic assembly, comprising: a microelectronic substrate; asupport member carrying the microelectronic substrate; and a connectionstructure carried by the support member, the connection structure havinga bond site configured to receive a flowable conductive material, theconnection structure further having at least two elongated membersconnected to and extending outwardly from the bond site with none of theelongated members being electrically coupled to the microelectronicsubstrate.
 41. The assembly of claim 40 wherein each elongated member isconfigured to receive at least a portion of the flowable conductivematerial from the bond site.
 42. The assembly of claim 40 wherein theconnection structure is a first connection structure and the elongatedmembers are first elongated members configured to receive at least aportion of a flowable conductive material from the first bond site, andwherein the apparatus further comprises a second connection structurecarried by the support member, the second connection structure having asecond bond site configured to receive a flowable conductive material,the second connection structure being electrically coupled to themicroelectronic substrate and having second elongated members extendingoutwardly from the second bond site, wherein each of the secondelongated members is configured to receive at least a portion of theflowable conductive material from the second bond site.
 43. The assemblyof claim 40 wherein the connection structure is a first connectionstructure and the elongated members are first elongated members, andwherein the apparatus further comprises a second connection structurecarried by the support member, the second connection structure having asecond bond site configured to receive a flowable conductive material,the second connection structure having a third bond site electricallycoupled to the microelectronic substrate, the second connectionstructure further having second elongated members extending outwardlyfrom the second bond site, wherein each of the second elongated membersis configured to receive at least a portion of the flowable conductivematerial from the second bond site, and wherein at least one of thesecond elongated members extends between the second and third bondsites.
 44. The assembly of claim 40 wherein the conductive structureincludes exactly two elongated members extending away from oppositesides of the bond site.
 45. The assembly of claim 40 wherein theconnection structure includes at least one electrically conductivemetallic material.
 46. The assembly of claim 40 wherein the bond siteincludes a solder ball pad, and wherein the apparatus further comprisesa solder ball disposed on the solder ball pad.
 47. The apparatus ofclaim 40 wherein the connection structure is a first connectionstructure and the elongated members are first elongated membersconfigured to receive at least a portion of a flowable material from thefirst bond site, and wherein the apparatus further comprises a secondconnection structure carried by the support member, the secondconnection structure having a second bond site configured to receive aflowable conductive material, the second connection structure beingelectrically coupled to the microelectronic substrate and having secondelongated members extending outwardly from the second bond site, whereineach of the second elongated members is configured to receive at least aportion of the flowable conductive material from the second bond site,and wherein the apparatus further comprises: a first solder balldisposed on the first bond site and projecting away from the first bondsite by a first distance; and a second solder ball disposed on thesecond bond site and projecting away from the second bond site by asecond distance at least approximately the same as the first distance.